HALO: an efficient global placement strategy for standard cells

This paper describes an efficient global cell (module) placement strategy called HALO (Hierarchical Alternating Linear Ordering) which generates a global 2-D placement of circuit modules by hierarchical application of linear ordering in alternating direction. It is explained why HALO should perform better than other typical, somewhat successful, analytical approaches such as min-cut, force-directed relaxation (FDR) or its likes. We have applied the HALO algorithm for standard cell placement. Experimental results on two benchmark circuits, primary1 and primary2 consisting of 752 and 2907 cells have shown a decrease of the half-perimeter routing lengths by 7% and 24% respectively, compared to the best available result^^^] obtained so far. Total CPU time including the following detailed placement was less than half of the earlier worklG].